1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to graphics frame buffer architecture.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
In order to provide memory systems with increased data handling rates and capacities, system architects may employ consistently higher levels of integration. One example of increased integration is the 3D-RAM family of memories from the Mitsubishi Corporation. The 3D-RAM incorporates four banks of DRAM main storage with level one and level two cache memories, and a bank-swapped shift register capable of providing an uninterrupted stream of sequential data at current pixel clock speeds.
Some previous incarnations of the 3D-RAM architecture have included cache management functions as well. In these older devices, circuitry was integrated to allow for the efficient write-back of modified or “dirty” data in the level one cache to the level two cache, and ultimately back to the DRAM. However, as these devices have grown in capacity and performance, it has become increasingly difficult and costly to integrate these cache management functions. In the most recent 3D-RAM device, the 3D-RAM64 these cache management functions have been abandoned altogether having finally become economically infeasible. Despite exclusion from the 3D-RAM devices, these cache management functions are still desirable as they may significantly increase memory performance by mitigating the penalties associated with level one cache misses. For these reasons, a system and method for externally managing the cache memory of 3D-RAM devices employed in graphics systems is desired.